Arithmetic logic units (ALUs) are electronic components that are used to perform specific arithmetic and logic functions. In general, an ALU is considered a part of the central processing unit (CPU) of a general purpose computer or of a micro-processor. Recently, computer designers and manufacturers have begun utilizing ALUs that are incorporated in digital signal processors (DSPs) to meet the demands of special applications, such as pattern recognition, digital image enhancement, radar processing, speech filtering, etc. The architecture of DSPs is particularly well-suited for computing-intensive applications that require frequent high-speed arithmetic operations. More specifically, DSPs are high-speed reduced-instruction-set devices which are capable of carrying out limited tasks such as addition, subtraction, multiplication, and shifting operations faster than general purpose processors. A typical DSP includes a micro-instruction sequencer, read-only-memory (ROM), random-access-memory (RAM), a high-speed ALU, a parallel multiplier, and related storage registers. The DSP controls the operation of the ALU through the micro-instruction sequencer.
Although ALUs are capable of performing standard arithmetic operations (e.g., addition, subtraction, and multiplication) in a single computing cycle they are unable to perform, with accuracy, other floating point arithmetic operations in a single clock cycle. A floating point (FP) format allows numbers to be represented in a large dynamic range and with high precision, which are critical for many applications. Due to the limitations of current ALUs, for many applications requiring floating point arithmetic operations, the computing algorithms are often cumbersome and complex because the necessary floating point arithmetic functions must be derived from a lengthy sequence of supported floating point or non-floating point computations.
It would be advantageous for an ALU to be able to perform floating point calculations in a single clock cycle. Furthermore, it would be advantageous for an ALU to be implemented with a floating point architecture that would allow the ALU to perform more functions than are currently available in a typical ALU. The types of functions needed to be performed in a floating point ALU include floating point multiplication, division, square root, logarithms, exponents, and MacLauren series expansions. Finally, such an implementation of a floating point ALU should be consistent with the industry standard 32 bit IEEE floating point format.
The application of the logarithm number (LN) format to perform arithmetic functions is well known in the art. The FP is analogous to the LN. To illustrate, in a digital computer with a 32 bit/word binary format, an FP includes the sign bit and two other parts: the first or exponent part typically uses eight (8) bits and represents the power to which one raises the number two in order to get the approximate number. The dynamic range of numbers that can be represented thus extends from zero all the way through the number two raised to the 128th power. This first exponent part is then multiplied by a second or mantissa part, which typically has twenty-three (23) bits in order to fully define the number. The mantissa is normalized so that it always lies within a limited range of values with the highest value being twice the lowest value, in keeping with the doubling of the number upon each increment of the exponent part.
Similarly, in the LN of the same number, the logarithm exponent is divided into a portion to the left of the decimal point that comprises whole or integer numbers called the characteristic, and a portion to the right of the decimal point called the fraction. It is known in the art that, in a LN of base two, the characteristic is the same as the FP exponent, and the fraction is nearly the same as the FP mantissa, assuming that certain normalization ranges are used. In short, the major difference between the FP and the corresponding LN of the same number is that the FP uses only integer exponents and spans the numbers in between with a linear fractional multiplier, whereas the LN utilizes a continuous spectrum of exponents to represent the number. Thus, the LN exponent need not be multiplied by a fractional quantity in order to fully define the number.
The similarity between the FP and the LN has made it common for FP algorithms to use the exponent and mantissa of FPs as rough guesses for the corresponding characteristic and fraction of LNs. U.S. Pat. No. 4,583,180, issued to Kmetz, discloses a digital transformation system for converting between FP and LN of the same number by normalizing the FP in the range of one to two, and adapting one function as the other function, after a correction, wherein the correction is generated by a ROM using the one function as an address. However, because the transformation taught by Kmetz apparently only approximates arithmetic operations, the results are not as accurate as full floating point arithmetic operations. For the purpose of the Kmetz method, apparently accuracy is not essential because such transformation is used for speech recognition signal analysis in which the results of many multiplications are averaged together so that accuracy is not contingent upon any one multiplication.
U.S. Pat. No. 4,720,809, issued to Taylor, discloses a hybrid FP/LN arithmetic processor. The patent discloses a hybrid arithmetic processor which combines attributes of conventional FP arithmetic with LN arithmetic. The arithmetic processor includes an input section for converting FP input operands to LN intermediate operands. A computing section performs arithmetic operations on the LN intermediate operands. An output section converts the LN intermediate output of the computing section to FP.
Taylor further discloses full look-up tables for converting from FP to LN. The look-up tables, as implemented in ROM, apparently require that the number of address lines be equal to the bit width of the input FP mantissa and the word length be equal to the bit width of the corresponding LN fraction. The Taylor method apparently requires a full mapping technique for converting from FP to LN. The full mapping technique requires a high utilization of ROM resources and is difficult to implement for a floating point format of 32-bit width, e.g., the IEEE floating point format.
Thus, there is a need in the art for improved speed and accuracy in performing floating point arithmetic operations.